EDN

Hierarchical timing analysis: Pros, cons, and a new approach

As digital semiconductor designs continue to grow larger, designers are looking to hierarchical methodologies to help alleviate huge runtimes. This approach allows designers to select and time certain ...
EDN

Hierarchical physical design—issues and methodologies

In IC physical design, there is a tendency to focus on the synthesis and layout tasks, and to not give much consideration to the chip finishing tasks, at least not until the more pressing matters of ...
Semiconductor Engineering

Efficient Hierarchical Verification For Low Power Designs

Growing design sizes, low power (LP) complexity and the need for early stage verification is making designers adopt hierarchical verification flows. Traditionally for hierarchical verification, ...
Electronic Design

Maximizing Hierarchical Design Throughput for Today’s Large Designs

Fig 1. As an example of today’s ASIC design complexity, IBM’s Cu-32 ASIC product offering delivers 2.9K raw gates per square millimeter. Such advanced process nodes enable SoC design teams to ...